Quadrupling code performance with a "useless" if.
Alisa Sireneva (12 July 2026)๐ https://purplesyringa.moe/blog/quadrupling-code-performance-with-a-useless-if/
โ #bcs #bcs1450
An interesting trick for increasing instruction-level parallelism by introducing a spurious-seeming conditional to break a dependency chain:
If we could tell the CPU to predict that
jstays intact, the loop would become throughput-bound rather than latency-bound. While we donโt have direct control over address prediction, we can simulate this with branch prediction: [โฆ]
See also Matt Godboltโs talk about the fundamental performance features of modern CPUs.
